Registration of New Students (UG) - 15 July 2024         Hostel Allottment List (Boys)                  Last Date for Application for BBA/MSc/MBA/MTech programs is 31 July 2024.                           Apply Online at www.getadmissions.com/jaypee

Jaypee Institute of Information Technology, Noida
  • JIIT
  • JIIT
  • JIIT
  • JIIT
  • Home
  • Dr. Satyendra Kumar
Associate Professor
satyendra.kumar@jiit.ac.in

Education

  • Ph.D. ECE (JIIT, Noida)
  • M.Tech. (IIT Roorkee)
  • B.E. (IIT Roorkee)

Biography

Satyendra Kumar received his B.E. degree in Electronics & communication Engineering from Indian Institute of Technology,Roorkee (Formerly University of Roorkee) and he is also received his M.Tech. degree from Indian Institute of Technology, Roorkee. He has completed his Ph.D. in SRAM design from department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India.

His professional experience includes semiconductor industry exposure on a number of projects for development and characterization of 90nm, 65nm and 55 nm memory compilers for different foundries like TSMC, IBM, UMC and others, and teaching experience as Assistant Professor, Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida.

Interest Area(s)

Modeling and Simulation of Semiconductor Devices, VLSI Circuit Design. SRAM Read and Write Assist Techniques For Low Power Applications, TFET Based SRAM Design.

Work Experience

21.5 yrs (Teaching+Research+Industry)

Publications

International Journals:

  • Singh K. S., Kumar S., "Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level," Journal of Circuits, Systems and Computers, Jan. 2024, doi: 10.1142/S0218126624502128

  • Verma P., Kumar S., "Investigation of In0.7Ga0.3As/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability," Journal of Circuits, Systems and Computers, Dec. 2023, doi: 10.1142/S0218126624501561

  • Verma, P., Nigam, K. & Kumar, S., “Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET,” Applied Physics A, 128, 955 (2022). https://doi.org/10.1007/s00339-022-06083-x

  • Dharmender, Nigam, K. & Kumar, S., “Performance assessment of cavity on source dual material split gate GaAs/InAs/Ge junctionless TFET for label-free detection of biomolecules,” Applied Physics A, 128, 943 (2022). https://doi.org/10.1007/s00339-022-06017-7    
  • Nigam, K., Kumar, S.,  Dharmender “Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET,” Journal of Computational Electronics, 2022, doi:10.1007/s10825-022-01902-z
  • Nigam, K., Kumar, S.,  Dharmender “Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET,” Journal of Computational Electronics, 2022, doi:10.1007/s10825-022-01902-z
  • Singh K. S., Kumar S.,Nigam  K.,"Design and Investigation of Dielectrically Modulated Dual-Material Gate-Oxide-Stack Double-Gate TFET for Label-Free Detection of Biomolecules,"IEEE Transactions on Electron Devices, vol. 68, no. 11, pp. 5784-5791, Nov. 2021, doi: 10.1109/TED.2021.3112639.
  • Kumar S., “Temperature dependence of analogue/RF performance, linearity and harmonic distortion for dual-material gate-oxide-stack double-gate TFET,” IET Circuits, Devices & Systems, March 2021,DOI:10.1049/cds2.12049
  • Kumar S.,Nigam K., Chaturvedi S., Khan A.I., Jain A.,“Performance Improvement of Double-Gate TFET Using Metal Strip Technique,” SiliconFebruary 2021, DOI:10.1007/s12633-021-00982-z
  • Nigam K., Kondekar P., Chandan B.V., Kumar S., et al. “Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor,” SiliconJanuary 2021, DOI:10.1007/s12633-021-00958-z
  • Kumar S., Singh K. S., Nigam  K., Chaturvedi S., “Ambipolarity Suppressed Dual-Material Double-Source T-Shaped Tunnel Field-Effect Transistor,” Silicon, vol. 13, no. 7, pp. 2065-2070 July 2020, DOI: 10.1007/s12633-020-00601-3
  • Nigam  K., Kumar S., Singh K. S., Bhardwaj E., Choubey S., Chaturvedi S.. “Temperature sensitivity analysis of SGO metal strip JL TFET,” IET Circuits, Devices & Systems, vol. 14, no. 4, pp. 444- 449, July 2020.
  • Singh K. S., Kumar S., Nigam  K., “Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET,” IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 404-412, June 2020, DOI: 10.1109/TDMR.2020.2984669.
  • Kumar S., Singh K. S., Nigam  K., Tikkiwal V.A. and Chandan  B.V.,“Dual- material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance,” Applied Physics A, vol. 125, no. 5, pp. 353- 360, May. 2019.
  • Chandan B.V., Gautami M., Nigam K., Sharma D., Tikkiwal V.A., Yadav S. and Kumar S., “Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance,” Journal of Computational Electronics, vol. 18, no. 1, pp. 76-82, Nov. 2018.
  • Kumar S., Saha K., Gupta H.O., “A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques,” Radioengineering, vol. 26, no. 3, pp. 772-780, 2017.
  • Kumar S., Saha K., Gupta H.O., “Study of SRAM Standby Leakage Reduction Techniques for Deep-submicron CMOS Technology,” International Journal of Control and Automation, vol. 10, no. 10, pp. 49-62,  2017.
  • Mehta,A., Kumar,S., Kumar,R., “A Novel Architecture and PVT Analysis of 4-Bit Manchester Carry Chain Block”, International Journal of Applied Engineering Research, vol.  9, no. 20, pp. 6581-6590,  2014.
  • Kumar, A., Kumar, S., Dubey, S., and Pandey, S. K., “A Novel Design of Fishnet Metamaterial Structure,” International Journal of Emerging Trends in Engineering and Development,” vol. 4, no. 2, pp. 201-204, May 2012.

International Conferences:

  • Kumar A., Kumar S., Chaturvedi S, "Simulation-Based Study of Gaussian-Doped Channel in Stacked Gate Oxide MOS Transistor," 2023 9th International Conference on Signal Processing and Communication (ICSC), NOIDA, India, 2023, pp. 774-777, doi: 10.1109/ICSC60394.2023.10441117

  • Bhaumik A. S., Kumar S., Chaturvedi S et al., "Reduction of Subthreshold Leakage Using Metal Strip in SGO Double-Gate MOSFET," 2023 9th International Conference on Signal Processing and Communication (ICSC), NOIDA, India, 2023, pp. 769-773, doi: 10.1109/ICSC60394.2023.10441253.

  • Singh K. S., Kumar S.,Nigam K.,"Tunnel Field Effect Transistor Based Biosensors: A Review," 2021 7th International Conference on Signal Processing and Communication (ICSC), 2021, pp. 391-395, doi: 10.1109/ICSC53193.2021.9673155.

  • Dharmender, Kumar S.,Nigam  K., "III-V / Si Heterojunction based Dual Material Stack Gate Oxide TFETs for Low Power Applications," 2021 7th International Conference on Signal Processing and Communication (ICSC), 2021, pp. 330-336, doi: 10.1109/ICSC53193.2021.9673374.
  • Verma P., Kumar S.,Nigam  K.,"Performance Analysis of Stack Gate Oxide Underlap TFET Utilising Metal Strip Mechanism," 2021 7th International Conference on Signal Processing and Communication (ICSC), 2021, pp. 372-376, doi: 10.1109/ICSC53193.2021.9673444.
  • Singh K. S., Kumar S.,Nigam  K., "Vertical Tunneling Based Dual-material Double-gate TFET," International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), 2021, pp. 900-904, doi: 10.1109/ICCCIS51004.2021.9397208.
  • Nishad D., Nigam K., Tikkiwal V.A., Kumar S.,"Performance Analysis of Double Gated GaAs-Ge Based Hetero Tunnel Field Effect Transistor," International Conference on Signal Processing and Communication (ICSC), 2020, pp. 284-287, doi: 10.1109/ICSC48311.2020.9182722.
  • Singh K. S., Kumar S., Nigam  K., Tikkiwal V.A.,“Tunnel Field Effect Transistor for Ultra Low Power Applications: A Review,” International Conference on Signal Processing and Communication (ICSC 2019), Noida, India,  pp. 286-291, 7-9 March 2019
  • Akhter S., Kumar S., D. Bareja, “Design and Analysis of Distributed Arithmetic based FIR Filter,” International Conference on Advances in Computing, Communication Control and Networking (ICACCCN 2018), pp. 721-726, July 2019.
  • Kumar S., Saxena, P., Tikkiwal, V.A., “SRAM Write Assist Techniques for Low Power Applications,” International Conference on Signal Processing and Communication (ICSC 2016), Noida, India, pp. 425-430, 26-28 Dec. 2016
  • Kumar S., Saha, K., Gupta, H., “Run Time Write Detection in SRAM,” International Conference on Signal Processing and Communication (ICSC-2015), Noida, India, pp 328-333, March 2015.
  • Kumar S., Tikkiwal,V.A., Gupta, H., “Read SNM free SRAM cell design in deep submicron technology,” International Conference on Signal Processing and Communication (ICSC-2013), Noida, India, pp 375-380, Dec 2013

PROFESSIONAL PROJECTS / PROFESSIONAL ACHIEVEMENTS

  • Rich experience of working in semiconductor industry as worked on development and characterization of 90 nm, 65 nm and 55 nm memory compilers for different customers like TSMC, IBM, UMC etc.
  • Reviewer of various reputed SCI international journals like IET Computers & Digital Techniques, IET Circuits, Devices & Systems, Applied Physics A, and Silicon.

SERVING AS REVIEWER:

  • IET Computers & Digital Techniques
  • IET Circuits, Devices & Systems
  • Applied Physics A
  • Silicon

ORGANIZED SEMINARS/CONFERENCES/WORKSHOPS

  • Webinar Series under the Alumni Connect Program, JIIT Noida, on May 2, 9,16, 2021 & June 6, 13, 20, 27, 2021.
  • One-week online program on “Technician Skill Development Program", JIIT,Sector-128, Noida, Nov. 2-7, 2020.
  • Webinar on “Technology Integration in Higher Education and National Education Policy-2020, JIIT, Sector-128, Noida, on Sept. 4, 2020.
  • Workshop on “Virtual Labs", at JIIT, Sector-128 campus, Noida, on Sept. 27,2019.
  • Two-day Workshop on “Low Voltage and Low Power VLSI Design", at JIIT, Sector-128 Campus, Noida, August 22 23, 2014.
  • Invited talk on “Data Compression - The Heart of Digital Revolution", delivered by Sh. R. K. Singh, Consultant (Technical and Programme), DUCR, University of Delhi, (Former Engineer-in-Chief, Doordarshan), at JIIT, Sector-128 campus, Noida, April 18, 2014.
  • Two week ISTE Workshop on “Signals & Systems", by IIT Kharagpur under MHRD programme, NMEICT, at JIIT, Sector-128 campus as remote center, Jan. 2 - 12, 2014.
  • Workshop on “COMSOL Multiphysics for MEMS modeling", at JIIT, Sector-128 campus, Noida, on Nov. 15, 2013.
  • Workshop on “Semiconductor Device Modeling using TCAD Tools", at JIIT, Sector-128 campus, Noida, on Oct. 4, 2013.
  • Three-day Workshop on “on Dot Net (Level 1)", at JIIT, Sector-62,Noida, June 5 - 7, 2013.
  • Workshop on “Virtual Labs", at JIIT, Sector-128 campus, Noida, on March 21, 2013.

SEMINARS/CONFERENCES/WORKSHOPS ATTENDED:

  • Five days FDP on “Recent Advances and Challenges in Nanoscale Devices: Design, Materials, and Applications Perspective", AICTE Training And Learning (ATAL) Academy, organized by NIT, Hamirpur (H.P.), June 1-5, 2021.
  • One-week online FDP on “Recent Trends in Photonics Technology", JIIT Sector-128, Noida, Dec. 28, 2020 Jan. 2, 2021.
  • One-week online FDP on “Artificial Intelligence and Machine Learning Using Python", JIIT Sector-128, Noida, Aug.10-15, 2020.
  • Five days International FDP on “Next Generation Semiconductor Devices:Modeling & Simulation", Microelectronics Research Group(MERG), KLEF, Vaddeswaram,Guntur, A.P., Aug. 4-8, 2020.
  • One week FDP on “Technology Computer Aided Design: Simulation for VLSI Devices, Circuits and Systems, JIIT, Sec.- 62, Noida, July 20-25, 2020.
  • International Conference On “Signal Processing And Communication (ICSC-2020)", JIIT, Sec.- 62, Noida, March 5- 7, 2020.
  • FDP on “Innovative Teaching Learning Methodologies, JIIT Sector-128, Noida, Dec 9-14, 2019.
  • Two day Workshop on “Emerging Computational Methods for Science and Engineering Applications", JIIT Sector-128, Noida, March 15- 16, 2019.
  • 5th International Conference on Signal Processing and Communication (ICSC-2019)", JIIT Noida, March 7- 9, 2019.
  • One week Faculty development program on “Recent Trends in Signal Processing, Microelectronics and Microwave, JIIT Sector-128, Noida, July 5 11, 2018.
  • Two-dayWorkshop on “Soft Computing and Language Processing", JIIT Sector-128, Noida, April 27- 28, 2018.
  • CSIR Sponsored workshop on “Recent trends in computational Physics", JIIT Sector-128, Noida, April 7- 8, 2018.
  • International Conference on “Signal Processing and Communication (ICSC-2018)", JIIT Noida, March 21-23, 2018.
  • One-day workshop on “GST Concept and Application", JIIT Sector-128, Noida, Dec. 9, 2017.
  • FDP on “Modelling and Simulation Tools in Electronics and Communication Engineering", JIIT Sector-128, Noida, July 10 -15, 2017.
  • Workshop on “Recent Trends in Mathematical Modelling and Scientific Computing", JIIT Sector-128, Noida, April 7- 8, 2017.
  • Short term training program on “CMOS, Mixed Signal and Radio Frequency VLSI Design", JIIT Sector-128, Noida, Jan. 30 - Feb. 4, 2017.
  • International Conference on “Signal Processing and Communication (ICSC-2016)", JIIT Noida, Dec. 26-28, 2016.
  • FDP on “Intelligent Systems and Automation Technology", JIIT Sector-128,Noida, June 20- 25, 2016.
  • FDP on “National Workshop on Computational Intelligence (NWCI-2016)", JIIT Sector-128, Noida, May 16- 28, 2016.
  • Workshop on “3G and 4G Systems-Working, planning and deployment scenario in India", JIIT Sector-128, Noida, April 8- 9, 2016.
  • National Workshop on “Information Security", JIIT Sector-128, Noida, Dec.22- 24, 2015.
  • FDP on “VLSI CAD TOOL", JIIT Sector-62, Noida, June 15- 20, 2015.
  • Synopsys University Symposium 2015 on “Electronic System Design and Prototyping: Tools & Methodologies", Synopsys and EIGEN Technologies Pvt. Ltd., New Delhi, April 30, 2015.
  • International conference on Signal Processing and Communication(ICSC-2015),JIIT Noida, March 16-18, 2015.
  • Workshop on "Statistical and Numerical Trends in Sciences and Engineering", JIIT Sector-128, Noida, Jan. 1, 2015.
  • IEEE SSCS Delhi Chapter “Distinguished Lecture Colloquia", ST Microelectronics Greater Noida, India, Dec. 19, 2014.
  • Two week ISTE Workshop on “Control Systems", by IIT Kharagpur under MHRD programme, NMEICT, held at JIIT Sector-128, Noida, Dec. 2- 12, 2014.
  • Workshop on “Low Voltage and Low Power VLSI Design", JIIT Sector-128, Noida, Aug. 22- 23, 2014.
  • Workshop on “Best Practices in Technical Education", JIIT Sector-62, Noida, March 15, 2014.
  • Synopsys University Symposium 2014 on “Custom IC Design & Device Modelling-Tools and Technologies", Synopsys and EIGEN Technologies Pvt. Ltd., New Delhi, March 7, 2014.
  • Two week ISTE Workshop on “Signals & systems", by IIT Kharagpur under MHRD programme, NMEICT, held at JIIT Sector-128, Noida, Jan. 2- 12, 2014.
  • International conference on Signal Processing and Communication(ICSC-2013),JIIT Noida, Dec. 12-14, 2013.
  • Workshop on “COMSOL Multiphysics for MEMS modeling", JIIT Sector-128, Noida, Nov. 15, 2013.
  • Workshop on “Semiconductor Device Modeling using TCAD Tools", JIIT Sector-128, Noida, Oct. 4, 2013.
  • Workshop on “Embedded Systems", JIIT Sector-62, Noida, July 1-5, 2013.
  • Workshop on “Digital System Testing" at JIIT Noida, July 23-27, 2013.
  • Workshop on “Virtual Labs" at JIIT Sector-128 Noida, March 21, 2013.
  • Workshop on “Super Attitude of Success" at JIIT Sector-128 Noida, Feb. 16, 2013.
  • Two-day ISTE Workshop on Aakash for Education by Indian Institute of Technology, Bombay (Under the National Mission on Education through ICT (MHRD, Govt. of India)), held at JIIT Sector-128 Noida, Nov. 10- 11, 2012.
  • Three-day International workshop MOS-AK/GSA India 2012 on “Device Modeling for Microsystems" at JIIT Noida, March 16-18, 2012.
  • Invited Talk on “Interface Physics Studies in Silicon Nano Devices" By Dr.M.K. Radakrishnan, Director, NanoRel- Technical Consultants, Singapore, JIIT Noida, Jan. 23, 2012