Admission Process Open for AY 2022-23.

Jaypee Institute of Information Technology, Noida
  • JIIT
  • JIIT
  • JIIT
Assistant Professor (Grade-II)
ankur.bhardwaj@jiit.ac.in

Education

  • B.tech(ECE) from G.B.T.U, Lucknow
  • M.tech(VLSI Design & Embedded Systems) from D.T.U, New Delhi

Interest Area(s)

Low Power Digital CMOS Design, Digital System Design using Verilog and Digital watermarking of sequential circuits.

Work Experience

Assistant Professor – II, JIIT, Sec 62 Noida,  (July 2013 – Present)

Publications

International Journal

  • A. Bhardwaj and S. Akhter,” Modified Counter Based Approach for Digital Watermarking of Sequential Circuits” International Journal of Innovative Technology and Exploring Engineering, Vol.8, June 2019, pp 3409-3413.
  • A.  Bhardwaj and S. Akhter, A Hardware Efficient Watermarking Technique Based on LFSR, International Journal of Recent Technology and Engineering, Vol. 8, pp. 3264-3268, 2019. 
  • M. Verma and A. Bhardwaj,”Implementation of FFT Architecture using Various Adders”,  International Journal of Innovative Technology and Exploring Engineering, Vol.8, pp. 3750-3755, 2019.
  • D. Sharma, A. Bhardwaj, H. Prasad, J. Kandpal, A. Saxena, K. Shashi Kant and G. Verma, “Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES”, International Journal of Security and Its Applications, vol 10, No. 7, pp. 11-24, August 2016.
  • S. Madhok, G. Verma, A. Bhardwaj, H. Verma, I. Singh and S. Shekhar,“Capacitance Scaling With Different IO Standard Based Energy Efficient Bio-Medical Wrist Watch Design on 28nm FGPA”, International Journal of Bio-Science and Bio-Technology,  Vol.7, No.4 (2015), pp.145-158.
  • J. Panda , A. Bhardwaj , N. Pandey and A. Bhattacharyya,”Hardware efficient watermarking technique for finite state sequential circuit using STG”,International Journal Of Innovative Research In Electrical, Electronics, Instrumentation And Control Engineering,  Vol. 2, Issue 7, July 2014.

International Conference

  • A. Bhardwaj and S. Akhter, "Multi Feedback LFSR Based Watermarking of FSM," 2021 7th International Conference on Signal Processing and Communication (ICSC), 2021, pp. 357-361, doi: 10.1109/ICSC53193.2021.9673360.
  • S. Akhter, S. Chaturvedi, S. Khan and A. Bhardwaj, "An Efficient CMOS Dynamic Logic-Based Full Adder," 2020 6th International Conference on Signal Processing and Communication (ICSC), 2020, pp. 226-229, doi: 10.1109/ICSC48311.2020.9182729.
  • A. Bhardwaj and S. Akhter,” IP Protection of Sequential Circuits Using Added States Watermark with Property Implantation”, Advances in Signal Processing and Communication- Select Proceedings of ICSC 2018, pp. 521-528.

WORKSHOPS AND CONFERENCES ATTENDED

  • Attended 6 days FDP on VLSI CAD tool conducted by ECE Department, JIIT Noida in June 2015.
  • Attended 3 days conference “ICSC-2015” organized by ECE Department, JIIT Noida in March 2015
  • Attended 6 days FDP on “Communication Engineering:Recent trends” conducted by ECE Department, JIIT Noida in July 2016.
  • Attended 6 days FDP on “Recent Trends in Signal Processing” conducted by ECE Department, JIIT Noida in July 2017.
  • Attended 2 days workshop on “Embedded Systems” conducted by ECE Department, JIIT Noida in July 2017
  • Attended International Conference on “Evolving Trends in Intelligent Management of the Future Grid” Sponsored by “Ministry of power, Govt. Of India”, INTELECT-2017, at Greater Noida in January 2017.
  • Attended 3 days conference “ICSC-2016” organized by ECE Department, JIIT Noida in December 2016.
  • Attended 3 days conference “ICSC-2017”organized by ECE Department, JIIT Noida in March 2017.