Spot Admission Open for few vacancies in BTech-ECE (Sector-128), Integrated MTech-ECE and Integrated MTech-Biotechnology (Sector-62).            JEE AIR / 10+2 Based Admission-Upgradation-8 (26 Nov 2021). Please check webportal.                                                                The Website of "SAI ADVANCE COVID CARE CENTRE” http://saiadvancecovidcarecentre.in at JIIT Campus, Sector-128, Wish Town Noida. ; a collaborative effort between JIIT Noida & Jaypee Hospital for welfare of society during pandemic is now live.

Jaypee Institute of Information Technology, Noida
  • Home
  • Dr. Kirmender Singh
Assistant Professor (Senior Grade)
Kirmender.singh@jiit.ac.in

Education

B.E, M.Tech, PhD

Biography

Kirmender singh completed his MTech in Microelectronics and Embedded technology from JIIT Noida and presently pursuing PhD. He have five year of industrial experience and three years of teaching experience prior to joining JIIT Noida in July 2004. Presently he is Assistant Professor in the Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Sector 62, Noida..

Interest Area(s)

VLSI

Work Experience

20 years (teaching+industry)

Publications:

International Journals:

  • Kirmender Singh, A .B. Bhattacharyya , “ Gummel Symmetry Test on charge based drain current expression using modified first-order hyperbolic velocity-field expression”, in journal of Solid State Electronics, Elsevier, Vol. 129, pp. 188-195, March 2015.
  • Kirmender Singh, “BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation using LM algorithm on 0.18µ technology node”,  International Journal of Electronics and Telecommunication, Vol. 64, No. 1, pp. 5-11, Feb 2018.

International Conferences:

  • K. Singh, A. B  Bhattacharyya “ Analysis of Second-order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror”, Proceeding of IEEE 28th International Conference on VLSI Design(VLSID),  Bangalore, Jan 3rd -7th , 2015 .
  • K. Singh , A. B. Bhattacharyya , “Transconductance Related Analysis of EKV MOSFET Model for a 0.35 μ CMOS Technology Node, IEEEProceedings of IEEE 17th International Conference on “Mixed Design of Integrated Circuits and Systems (MIXDES-2010)”, Wroclaw, Poland, June 24th -26th  2010.
  • A. B Bhattacharyya, K. Singh, “Transconductance Component Analysis of EKV MOSFET Model for CMOS Analog Design at 0.18μ Technology Node”,Sixth International Conference of Smart Material Structure and Systems(ISSS-2011),  Indian Institute of Science(IISC) Bangalore, Jan 4th-7th, 2012.
  • K. Singh, Paritosh Vyas, “Design Methodology of Standard Analog Circuit Block using EKV MOSFET Model and Validation using BSIM3v3 MOSFET Model”, International Conference on Signal Processing and Communication, Jaypee Institute of Information Technology (JIIT), 16th -18th  March, 2015.
  • ShikharTewari, K. Singh, “ Intuitive Design of PTAT and CTAT Circuits for MOSFET based temperature sensor using Inversion Coefficient based approach”, IEEE 19th International Symposium on VLSI Design and Test(VDAT-2015), Institute of Technology, Nirma University, Ahmedabad, 26th -29th June 2015

MISL:

  • Transconductance Related Analysis of EKV MOSFET Model for a 0.35 μ CMOS Technology Node “, K. Singh , A. B. Bhattacharyya . IEEE Proceedings of the 17th International Conference “Mixed Design of Integrated Circuits and Systems (MIXDES-2010)”, Wroclaw, Poland held on June 24-26 2010.
  • Transconductance Component Analysis of EKV MOSFET Model for CMOS Analog Design at 0.18μ Technology Node”, A. B. Bhattacharyya, K. Singh Sixth International Conference of Smart Material Structure and Systems(ISSS-2011) , Jan 4th -7th, 2012 , Indian Institute of Science(IISC) Bangalore.
  • K. Singh , A. B Bhattacharyya “ Analysis of Second-order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror”, IEEE 28th International Conference on VLSI Design(VLSID), Bangalore,( sister conferenceof IEEE DAC, DATE) Jan 3rd -7th , 2015 .
  • K. Singh, Paritosh Vyas, “Design Methodology of Standard Analog Circuit Block using EKV MOSFET Model and Validation using BSIM3v3 MOSFET Model”, International Conference on Signal Processing and Communication, Jaypee Institute of Information Technology (JIIT), 16th -18th March, 2015.
  • Shikhar Tewari, K. Singh, “ Intuitive Design of PTAT and CTAT Circuits for MOSFET based temperature sensor using Inversion Coefficient based approach”, IEEE 19th International Symposium on VLSI Design and Test(VDAT-2015), Institute of Technology, Nirma University, Ahmedabad, 26th -29th June 2015.