Dr. Ankur Bhardwaj - ASSISTANT PROFESSOR (SR GRADE)

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Dr. Ankur Bhardwaj

Biography

Dr. Ankur Bhardwaj is an Assistant Professor in the Department of Electronics and Communication Engineering at Jaypee Institute of Information Technology (JIIT), Noida, with over 12 years of experience in teaching and research. His specialization includes VLSI design and Embedded systems, Digital Watermarking of sequential circuits, and digital circuit design. He holds a Ph.D. in Electronics and Communication Engineering from JIIT, an M.Tech in VLSI Design and Embedded systems from D.T.U, Delhi, and a B.Tech in Electronics and Communication Engineering from GBTU. Dr. Ankur has published 5 research papers in indexed journals, contributed to book chapters, and presented his work at several international conferences. A dedicated mentor, Dr. Ankur has supervised M.Tech and B.tech students in their project work.

Research Highlights

Dr. Ankur Bhardwaj’s research focuses on IP protection of sequential circuits using digital watermarking. He has proposed several hardware efficient and secure watermarking techniques. Along with this, he has also worked in the field of digital circuit design and proposed an efficient architecture of circuits like CMOS based adder and FFT architecture.

Areas of Interest

VLSI design and Embedded systems
Digital Watermarking of sequential circuits
Low-Power Digital Circuit Design

Publications

Bhardwaj and S. Akhter,” Modified Counter Based Approach for Digital Watermarking of Sequential Circuits” International Journal of Innovative Technology and Exploring Engineering, Vol.8, June 2019, pp 3409-3413.
Bhardwaj and S. Akhter, “A Hardware Efficient Watermarking Technique Based on LFSR”, International Journal of Recent Technology and Engineering, Vol. 8, pp. 3264-3268, 2019.
Bhardwaj and S. Akhter, "Multi Feedback LFSR Based Watermarking of FSM," 2021 7th International Conference on Signal Processing and Communication (ICSC), 2021, pp. 357-361, doi: 10.1109/ICSC53193.2021.9673360.
Akhter, S. Chaturvedi, S. Khan and A. Bhardwaj, "An Efficient CMOS Dynamic Logic-Based Full Adder," 2020 6th International Conference on Signal Processing and Communication (ICSC), 2020, pp. 226-229, doi: 10.1109/ICSC48311.2020.9182729.
Bhardwaj and S. Akhter,” IP Protection of Sequential Circuits Using Added States Watermark with Property Implantation”, Advances in Signal Processing and Communication- Select Proceedings of ICSC 2018, pp. 521-528.