Have a Question about JIIT?
Chat with VIDYA
searchImportant Announcements:
Admissions Open for 2026.Apply NowAnother Opportunity : Open House (Parent Interaction) on 13th June 2026.Register NowCareer OpeningsApplyRound-1 of 10+2 Marks Based Counselling Scheduled for 03 June 2026. Instructions
Academic Experts
Dr. Saurabh Chaturvedi

Biography

Dr. Saurabh Chaturvedi is an Associate Professor in the Department of Electronics and Communication Engineering (ECE) at the Jaypee Institute of Information Technology (JIIT), Noida. He obtained a Ph.D. degree in Electronic Engineering from the University of Johannesburg (UJ), South Africa, in 2018; an M. Tech. degree in VLSI Design from the Centre for Development of Advanced Computing (CDAC), Noida, in 2008; and a B. Tech. degree in Electronics and Communication Engineering from JIIT, Noida, in 2005. During his doctoral program at UJ, Dr. Chaturvedi gained valuable international research exposure and collaborated with the National Institute for Research and Development in Microtechnologies, IMT Bucharest, Romania. He has over 18 years of professional experience spanning industry, academia, and research. Prior to joining JIIT, he worked with Cadence Design Systems, Mentor Graphics, and Essel Shyam Technologies. His research interests include microelectronics, nanoelectronics, VLSI design, nanoscale semiconductor devices, wireless communication systems, artificial intelligence, and machine learning. He has published extensively in reputed peer-reviewed international journals and conferences, and he is a Senior Member of IEEE.

Research Highlights

Dr. Saurabh Chaturvedi’s research focuses on integrated circuit design and simulation, modeling of advanced nanoscale semiconductor devices, and the application of machine learning and deep learning in electronics and communication. He has supervised doctoral research on deep learning techniques for enhancing the performance of wireless communication networks, as well as on the modeling and simulation of negative capacitance MOS devices for low-power applications. As an outcome of these research activities, he has co-authored several publications in reputed peer-reviewed international journals and conferences, along with patents. In addition, he actively engages in research with M. Tech. and B. Tech. students through their project work.

Areas of Interest
  • Microelectronics and Nanoelectronics
  • VLSI Design
  • Nanoscale Semiconductor Devices
  • Low-Power IC Design
  • Wireless Communication Systems
  • Machine Learning and Deep Learning
Patents
  • Title: Hybrid C-LSTM Network-based Channel Estimation for Polar Coded MIMO-OFDM System in 5G Networks
    Application Number: 202311059883 
    Status: Published (Oct. 2023)
  • Title: A Unified System and Method for Efficient Channel Estimation in Massive MIMO Networks
    Application Number: 202411070809
    Status: Published (Oct. 2024)