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Ms. Bhuvaneshwari shankar

Biography

Ms. Bhuvaneshwari is currently serving as an Assistant Professor in the Department of Electronics and Communication Engineering at Jaypee Institute of Information Technology, Noida, India. She is presently pursuing her Ph.D. in VLSI Nano-Scaled Device Design and Simulation (GAA-NS-FET) for Sensor-Based Applications at JIIT, Noida. She holds an M.Tech. in VLSI Design (Distinction) from Greater Noida Institute of Technology, Greater Noida, and a B.E. in Electronics and Communication Engineering from Anna University, Chennai.

She has more than three years of combined professional experience, including one year in academia and two years as a Mainframe Developer in the IT industry. Her academic and research training is enriched by faculty development programs from premier institutes, including IIT Kanpur, VIT Chennai, and NIT Warangal, focusing on Machine Learning, Nanoelectronics, and VLSI Sensor Technologies, Low Power Device Designing (CNTFETs).

Her primary research interests are in Nano-Scaled VLSI Device Modelling (GAAFET), Low-Power Circuit Design, HDL-based Hardware Implementation, and Electronic Devices & Circuits. She has published her work in reputed IEEE international conferences, including studies on CNTFET-based full adders and low-power multi-gate FET adders in 32nm technology.

Ms. Bhuvaneshwari is proficient in simulation and design tools such as TCAD Sentaurus and HSPICE, and she also holds certifications in IBM Mainframes (COBOL, CICS, JCL, VSAM), along with technical skills in VHDL, Microsoft Office, and Web Plot Digitizer. With a strong foundation in both teaching and applied research, she continues to contribute to advancing nanoelectronics and VLSI circuit design.

Educational Qualifications

Ph.D. (pursuing)in VLSI nano-scaled device-GAAFET designing and simulation in sensor based application from JIIT, Noida, M. Tech - Distinction. in VLSI Design- from Greater Noida Institute of Technology, Greater Noida, B.E-ECE from Anna University, Chennai

Research Highlights

Ms. Bhuvaneshwari’s research is focused on the design, simulation, and performance optimization of nano-scaled semiconductor devices with particular emphasis on Gate-All-Around Nanosheet FETs (GAANSFETs) and their applications in low-power VLSI circuits and sensor-based systems. Her work integrates device-level physics with circuit-level analysis, addressing challenges such as power consumption, leakage reduction, and improved switching characteristics in advanced transistor technologies.

Her contributions include the comparative analysis of CNTFET-based full adders and the design of low-power multi-gate FET adders, which highlight the advantages of novel transistor architectures in sub-32nm technology nodes. Through her ongoing doctoral research, she aims to develop optimized GAAFET architectures for highly efficient sensing applications, bridging the gap between device engineering and real-world electronic system integration.

Beyond devices, she is interested in HDL-based digital design, FETs device designing, and sensor circuits, with a vision of leveraging nanoelectronics for next-generation healthcare, environmental monitoring, and IoT-based smart systems. She continues to expand her expertise through FDPs and collaborations, and her proficiency in simulation environments such as TCAD Sentaurus and HSPICE allows her to explore new possibilities in nanoscale device modeling and circuit co-design.

Areas of Interest
  • VLSI (GAAFET) Nano-scaled Device Designing and simulation
  • HDL Designing
  • Electronics Devices & Circuits
  • TCAD and HSPICE Simulation
  • HDL-Based Digital Design (VHDL/Verilog)
  • Nanoelectronics for Sensors and IoT Applications
  • Low Power VLSI Circuit Design
Publications
  • Bhuvaneshwari, Shiv Narain Gupta, Priyesh Tiwari. “Comparative analysis of Full Adders using CNTFET in 32nm Technology.” In 2022 3rd International Conference on Intelligent Engineering and Management (ICIEM), pp. 279–284. IEEE, 2022.
  • Bhuvaneshwari, Shiv Narain Gupta, Priyesh Tiwari. “Low power adder using multi gate FET in 32nm technology.” In 2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE), pp. 1576–1579. IEEE, 2022.
  • Bhuvaneshwari, Archana Pandey,” Self-heating optimization of nanosheet field effect transistor performance with physics-based calibrated simulation setup in Pramana Journal of Physics” https://doi.org/10.1007/s12043-024-02883-3 Impact factor_2.2
  • Bhuvaneshwari, Archana Pandey, ”Structural Enhancements and Challenges from FINFET to 2D Material-Based GAANSFET: A Review” ICICCD_2024 https://www.scopus.com/freelookup/form/author.uri?zone=TopNavBar&origin=NO%20ORIGIN%20DEFINED