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Prof. Sajai Vir Singh

Biography

Prof. Sajai Vir Singh is a distinguished academic and researcher in the field of Electronics and Communication Engineering. He was born in Agra, India, and earned his Bachelor of Engineering degree in Electronics and Telecommunication from NIT Silchar (Assam), followed by M.Tech degree from MNIT Jaipur( Rajasthan). He completed his Ph.D. in 2011 from Uttarakhand Technical University. Currently, he is working as a Professor in the Department of Electronics and Communication Engineering at Jaypee Institute of Information Technology, Noida, India.

Prof. Singh has a robust teaching portfolio, covering a wide range of subjects at UG, PG and PhD level including Analog Electronics, Electrical Circuits Analysis, Semiconductor Physics, Signals and Systems, Digital Signal Processing, VLSI Design and Technology, CAD for ICs, VLSI Algorithms, Digital Integrated Circuits, VHDL Programming, Antenna and Wave Propagation, Analog CMOS Design, and Control Systems. His dedication to academia is reflected in his involvement with various institutional committees such as NBA and NAAC accreditation, curriculum design, quality assurance, anti-ragging, and examination moderation.

He is widely recognized for his research work, having authored nearly 100 research papers in prestigious international journals and conferences. His scholarly impact is evident not only in his publications but also in his ability to guide the next generation of researchers. Under his mentorship, five Ph.D. candidates have successfully completed their doctoral studies in various areas of VLSI design.

His expertise and scholarly contributions have made him a sought-after reviewer for numerous Ph.D. and M.Tech theses, as well as prestigious journals like IEEE Transactions on Circuits and Systems, Microelectronics Journal, Circuits, Systems and Signal Processing, Analog Integrated Circuits and Signal Processing, Journal of Circuits, Systems, and Computers, among others. Additionally, he has actively contributed to the organization of major IEEE conferences, serving as Technical Program Committee member, session chair, and organizing secretary for events including ICSC 2023 and ICSC 2025.

Prof. Singh’s multifaceted roles as an educator, researcher, reviewer, and organizer underscore his significant impact on the academic community and highlight his commitment to nurturing future leaders in electronics engineering.

Research Highlights

Prof. Sajai Vir Singh is a distinguished academician and researcher specializing in VLSI design. His primary research focus is on Low Power VLSI Circuits, including analog current mode filters, data converters, and SRAM design. He has also made significant advancements in the design and simulation of semiconductor devices with steep subthreshold slopes, particularly Tunnel Field-Effect Transistors (TFETs). Prof. Singh’s work on TFETs extends to their novel application as biosensors, showcasing his interdisciplinary approach bridging electronics and biomedical fields. With nearly 100 publications in reputed indexed international journals and conferences, his scholarly contributions are well recognized in the academic community. His research not only pushes the boundaries of low-power circuit design but also explores cutting-edge semiconductor technologies with potential real-world applications.

Areas of Interest
  • Current Mode Active Filter Circuits
  • Analog and Mixed Signal VLSI design Circuits
  • Data Converters
  • Modelling of Field effect transistors like TFETs
  • FinFets and TFET based Biosensors
  • Renewable energy
Publications

M. K. Bind, P. Kwatra, S. V. Singh*, K. Nigam and A. Patle, “Hydrogen gas (H2) sensor based on GaAs/GaSb heterojunction charge plasma TFET: A simulation study” Microsystem Technologies Journal, Vol. 32, Article No. 44 , March 2026, ISSN: -1432-1858, 10.1007/s00542-026-06036-x. 

P. Kwatra, S. V. Singh, M. K. Bind and K. Nigam, “Design and performance investigation of heterojunction electrically doped junction less TFET for label-free biomolecule detection considering ambipolar conduction”, Micro and Nanostructures, Vol. 211, Article No. 208564, March 2026, https://doi.org/10.1016/j.micrna.2026.208564. 

P. Kwatra, V. A. Tikkiwal , S. V. Singh and K. Nigam, “Design and investigation of novel heterojunction stacked oxide-dual tunneling FET assessing interface traps for improved reliability”, Physica Scripta, vol. 100(6), pp. 065019, 2025.

M. K. Bind, S. V. Singh, K. Nigam and Dharmender, “Work function engineered polarity-controlled TFET for digital circuit applications: design and performance analysis. Analog Integr Circ Sig Process 124, 41 (2025). https://doi.org/10.1007/s10470-025-02446-5.

M. K. Bind, S. V. Singh and K. Nigam, “Design and performance evaluation of a heterojunction GaAs/GaSb PC‑TFET for label‑free biosensing applications”, Journal of Electronic Materials, Vol. 54, pp. 1691-1708, 2025, ISSN: 0361-5235, https://doi.org/10.1007/s11664-024-11643-3.

M. K. Bind, S. V. Singh and K. Nigam, “GaAs//Ge polarity controlled TFET biosensor for SARS-CoV-2 detection: a simulation-based study”, Journal Microsystem Technologies, vol. 31, pp. 2067-2083, 2024, ISSN: 0946-7076, https://doi.org/10.1007/s00542-024-05836-3. 

M. K. Bind, S. V. Singh and K. Nigam, “Design and performance analysis of polarity control junction less TFET (PC-JLTFET) based biosensor”, Journal of Circuits, Systems and Computers, Vol.33 (17), pp. 2450302, 2024, ISSN: 1793-6454.

D. Basu, H. Mukherjee, M. Marciano, S. Sen, S.V. Singh, S. K. Md. Obaidullah and K. Roy “Bi-stage approach to North Indian raga distinction”, Multimedia Tools and Applications, Vol.83, pp.45163-45183, 2024, ISSN: 1573-7721, https://doi.org/10.1007/s11042-023-17322-5.  

P. Kwatra, S. V. Singh and K. Nigam “Performance and analysis of novel bilateral tunnelling based tunnel FET considering work function engineered metal strip for enhanced performance”, Microelectronics Journal, Vol.139, pp. 105878, Sept 2023, ISSN: - 0026-2692.

M. K. Bind, S. V. Singh and K. Nigam “Design and investigation of the DM‑ PC‑TFET‑based biosensor for breast cancer cell detection”, Transactions on Electrical and Electronic Materials, Vol. 24, pp. 381-395, July 2023, ISSN: - 2092-7592, https://doi.org/10.1007/s42341-023-00453-9.

P. Kwatra, S. V. Singh and K. Nigam “Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor”, Microelectronics Reliability, Vol.140, pp. 114872, Jan 2023, ISSN: - 0026-2714.

P. Kwatra, K. Nigam and S. V. Singh, “Design and performance evaluation of a novel dual tunneling based TFET considering trap charges for reliability improvement”, Silicon Journal, Vol. 15, pp. 2407-2425, 2023, ISSN:-1876-9918, https://doi.org/10.1007/s12633-022-02188-3. 

M. K. Bind, K. Nigam, S. V. Singh, “Sensitivity assessment of electrically doped cavity on source tunnel field effect junction less transistor-based biosensor”, Journal of Circuits, Systems and Computers, Vol. 32, pp. 2350018, Jan 2023, ISSN: 1793-6454. 

S. A. Barlaskar, S. V. Singh, A. Monsley and R. H. Laskar, “Genetic algorithm based optimized watermarking technique using hybrid DCNN-SVR and statistical approach for watermark extraction”, Multimedia Tools and Applications, Vol. 81, pp. 7461-7500, 2022, ISSN: 1573-7721, https://doi.org/10.1007/s11042-021-11798-9. 

K. Nigam, S. V. Singh and P. Kwatra, “Investigation and design of stacked oxide polarity gate JLTFET in the presence of interface trap charges for Analog/RF applications”, Silicon Journal, Vol. 14, pp. 3963-3980, 2022, ISSN:-1876-9918, https://doi.org/10.1007/s12633-021-01162-9.

Dipti, S.V. Singh, T. Kumawat, A. Bekal, P. K. Mishra and M. Goswami, “A 13.8 pJ/conv-step binary search ADC with reusable comparator architecture”, International Journal of Electronics and Communication (AEU), Vol. 144, 2022, 154056, ISSN 1434-8411, https://doi.org/10.1016/j.aeue.2021.154056.

S. V. Singh, R. S. Tomar and M. Goswami, “A current tunable mixed-mode ZC-CCTAs based resistor less universal filter”, Journal of Circuits, Systems and Computers, Vol. 30(12) 20150225(24 Pages), 2021, ISSN: 1793-6454, https://doi.org/10.1142/S021812662150225X.

C. Shankar, S. V. Singh and R. Imam “SIFO-VM/TIM universal biquad filter using single DVCCTA with fully CMOS realization”, Analog Integrated Circuits and Signal Processing, Vol. 109, pp. 33-46, 2021, ISSN: 0925-1030, doi.org/10.1007/s10470-021-01900-4. 

D. Kumar, R. Anand, S. V. Singh, P. K.  Mishra, A. Srivastava, and M. Goswami, “A 0.4 mW, 0.27 pJ/Bit true random number generator using jitter, metastability and current starved topology”, IET Circuits, Devices and Systems, UK, Vol. 14 (7), pp. 1001-1011, 2020, ISSN: -1751-8598, doi: 10.1049/iet-cds.2019.0318.

Dipti, S.V. Singh, R. Joshi, P. K. Mishra and M. Goswami, “A reusable stage based reduced comparator count binary search ADC”, Analog Integrated Circuits and Signal Processing, Vol. 105, pp. 33-43, 2020, ISSN 0925-1030.