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Jaypee Institute of Information Technology, Noida
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  • Dr. Archana Pandey
Assistant Professor (Senior Grade)
archana.pandey@jiit.ac.in

Education

  • PhD, Title: “Impact of FinFET Parasitic Effects in Circuit Design”, Indian Institute of Technology, Roorkee
  • M.Tech, Solid state Electronic Materials, Indian Institute of Technology, Roorkee
  • B.Tech, Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri

Research Area:

Novel semiconductor devices, FinFETs, Device modeling, Delay modeling of Digital circuit modules, Digital VLSI circuit design, VLSI device-circuit co-design.

Publications

International Journals:

  • A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, “Effect of load capacitance and input transition time on FinFET inverter capacitances,” IEEE Transactions on Electron Devices, vol. 61, no. 1, pp. 30-36, 2014.
  • A. Pandey, H. Kumar, S. K. Manhas, S. Dasgupta, and B. Anand, “Atypical Voltage transitions in FinFET Multi- Stage Circuits : Origin and Significance,” IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1392-1396, March 2016.

International Conferences:

Book Chapter:

Saurabh K. Nema, M. SaiKiran (2), P. Singh (2), Archana Pandey (2), S. K. Manhas (2), A. K. Saxena (2), Anand Bulusu (2)“Improved Underlap FinFET with Asymmetric Spacer Permittivities” in Physics of Semiconductor Devices. Springer, Cham, DOI (Digital   ObjectIdentifier):10.1007/9783319030029_67.

Academic Achievements:

  • Second position in state (Uttarakhand, India) in Intermediate Uttarakhand Board
  • Got Merit scholarship in all the four years of B. Tech
  • Qualified GATE examination with 99.08 percentile

Technical Exposure:

Simulation Tools: 6 year experience of TCAD Sentaurus (Sentaurus structure editor, Sdevice, Sprocess, Tecplot, Svisual, Inspect), TSPICE, HSPICE, MATLAB