- PhD, Title: “Impact of FinFET Parasitic Effects in Circuit Design”, Indian Institute of Technology, Roorkee
- M.Tech, Solid state Electronic Materials, Indian Institute of Technology, Roorkee
- B.Tech, Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri
Novel semiconductor devices, FinFETs, Device modeling, Delay modeling of Digital circuit modules, Digital VLSI circuit design, VLSI device-circuit co-design.
- A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, “Effect of load capacitance and input transition time on FinFET inverter capacitances,” IEEE Transactions on Electron Devices, vol. 61, no. 1, pp. 30-36, 2014.
- A. Pandey, H. Kumar, S. K. Manhas, S. Dasgupta, and B. Anand, “Atypical Voltage transitions in FinFET Multi- Stage Circuits : Origin and Significance,” IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1392-1396, March 2016.
- A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, “FinFET device capacitances: Impact of input transition time and output load,” in Proc. IEEE 5th International Nanoelectronics Conference (INEC), Singapore, Jan. 2013, pp. 393-395.
- A. Pandey, H. Kumar, P. Goyal, S. Dasgupta, S. K. Manhas and B. Anand, “FinFET Device Circuit Co-design Issues : Impact of Circuit Parameters on Delay,” in Proc. IEEE VLSI Design, Kolkata, Jan. 2016, pp. 288-293.
- A. Pandey, P. Garg, S. Tyagi, R. Ranjan and B. Anand, “A modified method of logical effort for FinFET circuits considering impact of fin-extension effects” in Proc. 19th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, Mar. 2018, 189-195.
Saurabh K. Nema, M. SaiKiran (2), P. Singh (2), Archana Pandey (2), S. K. Manhas (2), A. K. Saxena (2), Anand Bulusu (2)“Improved Underlap FinFET with Asymmetric Spacer Permittivities” in Physics of Semiconductor Devices. Springer, Cham, DOI (Digital ObjectIdentifier):10.1007/9783319030029_67.
- Second position in state (Uttarakhand, India) in Intermediate Uttarakhand Board
- Got Merit scholarship in all the four years of B. Tech
- Qualified GATE examination with 99.08 percentile
Simulation Tools: 6 year experience of TCAD Sentaurus (Sentaurus structure editor, Sdevice, Sprocess, Tecplot, Svisual, Inspect), TSPICE, HSPICE, MATLAB