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Jaypee Institute of Information Technology, Noida
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  • Dr. Satyendra Kumar
Assistant Professor (Senior Grade)
satyendra.kumar@jiit.ac.in

Education

  • Ph.D. ECE (JIIT, Noida)
  • M.Tech. (IIT Roorkee)
  • B.E. (IIT Roorkee)

Biography

Satyendra Kumar received his B.E. degree in Electronics & communication Engineering from Indian Institute of Technology,Roorkee (Formerly University of Roorkee) and he is also received his M.Tech. degree from Indian Institute of Technology, Roorkee. He has completed his Ph.D. in SRAM design from department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India.

His professional experience includes semiconductor industry exposure on a number of projects for development and characterization of 90nm, 65nm and 55 nm memory compilers for different foundries like TSMC, IBM, UMC and others, and teaching experience as Assistant Professor, Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida.

Interest Area(s)

Modeling and Simulation of Semiconductor Devices, VLSI Circuit Design. SRAM Read and Write Assist Techniques For Low Power Applications, TFET Based SRAM Design.

Work Experience

19 yrs (Teaching+Research+Industry)

Publications

International Journals:

  • Kumar S.,Nigam K., Chaturvedi S., Khan A.I., Jain A.,“Performance Improvement of Double-Gate TFET Using Metal Strip Technique,” Silicon, February 2021, DOI:10.1007/s12633-021-00982-z
  • Nigam K., Kondekar P., Chandan B.V., Kumar S., et al. “Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor,” Silicon, January 2021, DOI:10.1007/s12633-021-00958-z
  • Kumar S., Singh K. S., Nigam  K., Chaturvedi S., “Ambipolarity Suppressed Dual-Material Double-Source T-Shaped Tunnel Field-Effect Transistor,” Silicon, vol. 13, no. 7, pp. 2065-2070 July 2020, DOI: 10.1007/s12633-020-00601-3 (Accepted)
  • Nigam  K., Kumar S., Singh K. S., Bhardwaj E., Choubey S., Chaturvedi S.. “Temperature sensitivity analysis of SGO metal strip JL TFET,” IET Circuits, Devices & Systems, vol. 14, no. 4, pp. 444- 449, July 2020.
  • Singh K. S., Kumar S., Nigam  K., “Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET,” IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 404-412, June 2020, DOI: 10.1109/TDMR.2020.2984669.
  • Kumar S., Singh K. S., Nigam  K., Tikkiwal V.A. and Chandan  B.V.,“Dual- material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance,” Applied Physics A, vol. 125, no. 5, pp. 353- 360, May. 2019.
  • Chandan B.V., Gautami M., Nigam K., Sharma D., Tikkiwal V.A., Yadav S. and Kumar S., “Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance,” Journal of Computational Electronics, vol. 18, no. 1, pp. 76-82, Nov. 2018.
  • Kumar S., Saha K., Gupta H.O., “A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques,” Radioengineering, vol. 26, no. 3, pp. 772-780, 2017.
  • Kumar S., Saha K., Gupta H.O., “Study of SRAM Standby Leakage Reduction Techniques for Deep-submicron CMOS Technology,” International Journal of Control and Automation, vol. 10, no. 10, pp. 49-62,  2017.
  • Mehta,A., Kumar,S., Kumar,R., “A Novel Architecture and PVT Analysis of 4-Bit Manchester Carry Chain Block”, International Journal of Applied Engineering Research, vol.  9, no. 20, pp. 6581-6590,  2014.
  • Kumar, A., Kumar, S., Dubey, S., and Pandey, S. K., “A Novel Design of Fishnet Metamaterial Structure,” International Journal of Emerging Trends in Engineering and Development,” vol. 4, no. 2, pp. 201-204, May 2012.

International Conferences:

  • Singh K. S., Kumar S.,Nigam  K., "Vertical Tunneling Based Dual-material Double-gate TFET," International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), 2021, pp. 900-904, doi: 10.1109/ICCCIS51004.2021.9397208.
  • Nishad D., Nigam K., Tikkiwal V.A., Kumar S.,"Performance Analysis of Double Gated GaAs-Ge Based Hetero Tunnel Field Effect Transistor," International Conference on Signal Processing and Communication (ICSC), 2020, pp. 284-287, doi: 10.1109/ICSC48311.2020.9182722.
  • Singh K. S., Kumar S., Nigam  K., Tikkiwal V.A.,“Tunnel Field Effect Transistor for Ultra Low Power Applications: A Review,” International Conference on Signal Processing and Communication (ICSC 2019), Noida, India,  pp. 286-291, 7-9 March 2019
  • Akhter S., Kumar S., D. Bareja, “Design and Analysis of Distributed Arithmetic based FIR Filter,” International Conference on Advances in Computing, Communication Control and Networking (ICACCCN 2018), pp. 721-726, July 2019.
  • Kumar S., Saxena, P., Tikkiwal, V.A., “SRAM Write Assist Techniques for Low Power Applications,” International Conference on Signal Processing and Communication (ICSC 2016), Noida, India, pp. 425-430, 26-28 Dec. 2016
  • Kumar S., Saha, K., Gupta, H., “Run Time Write Detection in SRAM,” International Conference on Signal Processing and Communication (ICSC-2015), Noida, India, pp 328-333, March 2015.
  • Kumar S., Tikkiwal,V.A., Gupta, H., “Read SNM free SRAM cell design in deep submicron technology,” International Conference on Signal Processing and Communication (ICSC-2013), Noida, India, pp 375-380, Dec 2013.

PROFESSIONAL PROJECTS / PROFESSIONAL ACHIEVEMENTS

  • Rich experience of working in semiconductor industry as worked on development and characterization of 90 nm, 65 nm and 55 nm memory compilers for different customers like TSMC, IBM, UMC etc.
  • Reviewer of various reputed SCI international journals like IET Computers & Digital Techniques, IET Circuits, Devices & Systems, Applied Physics A, and Silicon.