Jaypee Institute of Information Technology, Noida
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  • Dr. Saurabh Chaturvedi
Assistant Professor (Senior Grade)
saurabh.chaturvedi@jiit.ac.in, chaturvedi.s.in@ieee.org

Education

  • Ph.D. (Electrical and Electronic Eng.), University of Johannesburg, Johannesburg, 2015-2018
  • M.Tech. (VLSI Design), Centre for Development of Advanced Computing (CDAC), NOIDA; Guru Gobind Singh IP University, Delhi, 2006-2008
  • B.Tech. (Electronics and Comm. Eng.), Jaypee Institute of Information Technology (JIIT), NOIDA, 2001-2005

Professional Experience

  • Assistant Professor, Department of Electronics and Comm. Eng., JIIT, NOIDA, Jun. 2018-Present
  • Visiting Researcher, National Institute for Research and Development in Microtechnologies, IMT Bucharest, Romania, Oct.-Dec. 2016 and Oct.-Dec. 2017 
  • Assistant Professor, Department of Electronics and Comm. Eng., JIIT, NOIDA, Jul. 2009-Apr. 2015
  • Consultant, Cadence Design Systems, NOIDA, May 2008-Jul. 2009
  • Intern, Mentor Graphics, NOIDA, Dec. 2007-Apr. 2008
  • Hub and RF Engineer, Essel Shyam Technologies, NOIDA, Jun. 2005-Jul. 2006

Professional Membership

IEEE Senior Member

Interest Areas

Microelectronics and VLSI design, Microwave and millimetre-wave IC design, RF MEMS

Doctoral Thesis Title

BiCMOS Millimetre-wave Active Bandpass Filter

Publications

Refereed/Peer-Reviewed International Journals:         

  • J. D. Yadav, V. K. Dwivedi, and S. Chaturvedi, “ResNet-enabled cGAN model for channel estimation in massive MIMO system," Wireless Communications and Mobile Computing, vol. 2022, pp. 1-9, Aug. 2022, DOI: https://doi.org/10.1155/2022/2697932
  • A. Upadhya, M. Meenalakshmi, S. Chaturvedi, and V. K. Dwivedi, “Full duplex mixed FSO/RF relaying systems with self-interference and outdated CSI,” Optical and Quantum Electronics, Oct. 2022, DOI: 10.1007/s11082-022-04265-8
  • M. Meenalakshmi, S. Chaturvedi, and V. K. Dwivedi, “Deep learning techniques for OFDM systems,” IETE Journal of Research, Oct. 2021.
  • S. Kumar, K. Nigam, S. Chaturvedi, A.I. Khan, and A. Jain, “Performance improvement of double-gate TFET using metal strip technique,” Silicon, Feb. 2021.
  • S. Kumar, S. Singh, K. Nigam, and S. Chaturvedi, “Ambipolarity suppressed dual-material double-source T-shaped tunnel field-effect transistor,” Silicon, vol. 13, pp. 2065-2070, Jul. 2020.
  • S. Chaturvedi, M. Božanić, and S. Sinha, “60 GHz BiCMOS active bandpass filters,” Microelectronics Journal, vol. 90, pp. 315-322, Jul. 2019.
  • T. Gupta, S. Akhter, S. Khan, and S. Chaturvedi, “Multiplication technique in residue number system,” International Journal of Engineering and Advanced Technology, vol. 8, no. 6, pp. 1037-1041, Aug. 2019.
  • T. Gupta, S. Akhter, A. Srivastava, and S. Chaturvedi, “HDL implementation of five moduli residue number system,” International Journal of Innovative Technology and Exploring Engineering, vol. 8, no. 9, pp. 689-693, Jul. 2019
  • S. Chaturvedi, M. Božanić, and S. Sinha, “Millimeter wave passive bandpass filters,” Microwave Journal, vol. 60, no. 1, pp. 98-108, Jan. 2017.
  • S. Chaturvedi, M. Božanić, and S. Sinha, “Millimeter wave active bandpass filters,” Microwave Journal, vol. 60, no. 2, pp. 76-88, Feb. 2017.
  • S. Chaturvedi, M. Božanić, and S. Sinha, “Extraction of transmission line parameters and effect of conductive substrates on their characteristics,” Romanian Journal of Information Science and Technology, vol. 19, no. 3, pp. 199-212, 2016.
  • S. Akhter and S. Chaturvedi, “A high speed 14 transistor full adder cell using novel 4 transistor XOR/XNOR gates based on dynamic CMOS logic,” International Journal of Applied Engineering Research, vol. 9, no. 11, pp. 1551-1564, May 2014.
  • A. K. Srivastava, S. Chaturvedi, and H. O. Gupta, “On Xilinx design language format for reconfigurable evolvable hardware,” International Journal of Applied Engineering Research, vol. 9, no. 11, pp. 1591-1602, May 2014.
  • S. Chaturvedi, A. K. Srivastava, N. Bisht, and P. Khanna, “A novel edge detection based technique for fingerprint recognition,” International Journal of Applied Engineering Research, vol. 9, no. 19, pp. 5847-5856, Aug. 2014.

Refereed/Peer-Reviewed International and National Conferences:

  • M. Meenalakshmi, S. Chaturvedi, and V. K. Dwivedi, “Deep learning-based channel estimation in 5G MIMO-OFDM systems,” IEEE 2022 8th International Conference on Signal Processing and Communication (ICSC 2022), Dec. 2022, NOIDA, India.
  • M. Meenalakshmi, S. Chaturvedi, and V. K. Dwivedi, “Performance analysis of polar codes in 5G new radio,” IEEE 2021 7th International Conference on Signal Processing and Communication (ICSC 2021), pp. 96-99, Nov. 2021, NOIDA, India.
  • J. Yadav, V. K Dwivedi, and S. Chaturvedi, “Performance comparison of cGAN models for channel estimation in one-bit massive MIMO system,” 2021 IEEE Workshop on Microwave Theory and Techniques in Wireless Communications (MTTW'21), pp. 296-300, Oct. 2021, Riga, Latvia.
  • S. Akhter, S. Chaturvedi, S. Khan, and A. Bhardwaj, “An efficient CMOS dynamic logic-based full adder,” IEEE 6th International Conference on Signal Processing and Communication (ICSC 2020), Mar. 2020, NOIDA, India.
  • S. Chaturvedi, V. Sharma, N. Singh, and S. Akhter, “Progress and advancements in tunnel FET technology,” IEEE 6th International Conference on Signal Processing and Communication (ICSC 2020), Mar. 2020, NOIDA, India. 
  • S. Akhter, S. Chaturvedi, and S. Khan, “A distinctive approach for Vedic-based squaring circuit,” IEEE 7th International Conference on Signal Processing and Integrated Networks (SPIN 2020), Feb. 2020, NOIDA, India. 
  • A. Jain, S. Bansal, S. Akhter, S. Chaturvedi, and S. Khan, “Implementation of an efficient N×N multiplier based on Vedic mathematics and Booth-Wallace tree multiplier,” IEEE International Conference on Power Electronics, Control and Automation (ICPECA), pp. 1-5, Nov. 2019, Delhi, India. 
  • S. Akhter and S. Chaturvedi, “Modified binary multiplier circuit based on Vedic mathematics,” IEEE 6th International Conference on Signal Processing and Integrated Networks (SPIN 2019), pp. 234-237, Mar. 2019, NOIDA, India. 
  • N. Singh, S. Chaturvedi, and S. Akhter, “Weather forecasting using machine learning algorithm,” IEEE 5th International Conference on Signal Processing and Communication (ICSC 2019), pp. 171-174, Mar. 2019, NOIDA, India. 
  • S. Chaturvedi, M. Božanić, and S. Sinha, “Implementation of a 6 GHz MEMS switch,” IEEE 3rd International Symposium on Nanoelectronic and Information Systems (iNIS 2017), pp. 74-77, Dec. 2017, Bhopal, India.
  • S. Chaturvedi, M. Božanić, D. Vasilache, S. Sinha, I. Giangu, and A. Stefanescu, “Cantilever for RF applications: Model and technology,” IEEE 40th International Semiconductor Conference (CAS 2017),    pp. 271-274, Oct. 2017, Sinaia, Romania.
  • S. Chaturvedi, M. Božanić, and S. Sinha, “A 50 GHz SiGeBiCMOS active bandpass filter,” IEEE 20th  International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), pp. 2-5, Apr. 2017, Dresden, Germany.
  • M. Božanić, S. Chaturvedi, and S. Sinha, “Re-inventing postgraduate level teaching and learning in nanoelectronics,” IEEE 13th AFRICON (AFRICON 2017), pp. 676-681, Sep. 2017, Cape Town, South Africa.
  • M. Božanić, S. Chaturvedi, and S. Sinha, “Evolving the BRICS multi-lateral qualification through online education innovation,” International Conference on Empowerment through Education, Ethics & Entrepreneurship (IC-4E) - The Next Agenda for BRICS, pp. 25-29, Feb. 2017, Mandsaur, India.
  • S. Chaturvedi, M. Božanić, and S. Sinha, “Comparison of Al and Cu interconnects using VHDL-AMS and SPICE modeling,” IEEE 2nd International Conference on Contemporary Computing and Informatics (IC3I 2016), pp. 590-593, Dec. 2016, NOIDA, India.
  • S. Chaturvedi, M. Božanić, and S. Sinha, “Effect of lossy substrates on series impedance parameters of interconnects,” IEEE 39th International Semiconductor Conference (CAS 2016), pp. 55-58, Oct. 2016, Sinaia, Romania.
  • S. Akhter, S. Chaturvedi, and K. Pardhasardi, “CMOS implementation of efficient 16-bit square root carry-select adder,” IEEE 2nd International Conference on Signal Processing and Integrated Networks (SPIN 2015), pp. 891-896, Feb. 2015, NOIDA, India.
  • S. Akhter and S.Chaturvedi,“HDL based implementation of N×N bit-serial multiplier,” IEEE International Conference on Signal Processing and Integrated Networks (SPIN 2014), pp. 470-474, Feb. 2014, NOIDA, India.
  • S. Akhter and S.Chaturvedi, “A novel method for dual output dynamic logic using SCL topology,” IEEE International Conference on Signal Processing and Integrated Networks (SPIN 2014), pp. 481-485, Feb. 2014, NOIDA, India.
  • A. K. Srivastava, A. Gupta,S.Chaturvedi, and V. Rastogi, “Design and simulation of virtual reconfigurable circuit for a fault tolerant system,” IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE 2014), pp. 1-4, May 2014, Jaipur, India.
  • A. K. Srivastava, S. Madan, S.Chaturvedi,and H. O. Gupta,  “Synthesis of evolvable hardware with different clustering techniques,” 5th International Conference on Computer Applications in Electrical Engineering - Recent Advances (CERA 2013), pp. 306-310, Oct. 2013, Roorkee, India.
  • S. Chaturvediand A. Noor, “Design rule checking at the register transfer level: A case study,” National Conference on Emerging Technologies (NCET 2009), pp. 1-4, Jan. 2009, Moradabad, India.

Awards and Achievements

  • Global Excellence and Stature (GES) scholarship was awarded for three years (2015-2018) by the University of Johannesburg for doctoral studies.
  • Merit scholarship was awarded for three years (2015-2018) by the University of Johannesburg during doctoral studies. 
  • Elevated to the IEEE Senior Member grade in Apr. 2017.
  • Selected for the South African National Research Foundation (NRF) and Department of Science and Technology (DST) Innovation doctoral scholarship award for three years in 2015.
  • Participated in two research visits to the National Institute for Research and Development in Microtechnologies, IMT Bucharest, Romania from Oct.-Dec. 2016 and Oct.-Dec. 2017 to partake in international mobility under the science and technology bilateral agreement between South Africa and Romania for the two-year NRF/UEFISCDI cooperation project through the NRF, South Africa grant.
  • International travel grant was awarded by the University of Johannesburg for attending and presenting a paper at IEEE 3rd International Symposium on Nanoelectronic and Information Systems (iNIS 2017), Bhopal, India in Dec. 2017.
  • International travel grant was awarded by the NRF, South Africa for attending and presenting a paper at IEEE 40th International Semiconductor Conference (CAS 2017), Sinaia, Romania in Oct. 2017.
  • International travel grant was awarded by the University of Johannesburg for attending and presenting a paper at IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), Dresden, Germany in Apr. 2017.   
  • International travel grant was awarded by the NRF, South Africa for attending and presenting a paper at IEEE 39th International Semiconductor Conference (CAS 2016), Sinaia, Romania in Oct. 2016.
  • International travel grant was awarded by the University of Johannesburg for attending and presenting a paper at IEEE 2nd International Conference on Contemporary Computing and Informatics (IC3I 2016), NOIDA, India in Dec. 2016.
  • Graduate Aptitude Test in Engineering (GATE) scholarship was awarded by the Ministry of Human Resource Development (MHRD), Government of India during the M. Tech. programme (2006-2008).
  • Associated and worked for the book ‘Compact MOSFET models for VLSI design’, authored by Prof A. B. Bhattacharyya and published by John Wiley & Sons, Singapore and IEEE Press, 2009. The contribution was acknowledged in the book.
  • Technical reviewer of International Journal of Electronics, IEEE Consumer Electronics Magazine, IEEE SAIEE Africa Research Journal, International Journal of Advanced Computer Science and Applications, IEEE ICSC and IEEE SPIN conferences.
Dr. Saurabh Chaturvedi - Assistant Professor (Senior Grade) in JIIT

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