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  • Dr. Shruti Kalra
Assistant Professor (Senior Grade)


PhD (Microelectronics), M.Tech (VLSI Design), B.Tech (Electronics and Communication)


Done B.Tech in Electronics and communication from UPTU in 2005,M.Tech in VLSI Design from CDAC, Noida in 2007 and PhD in Microelectronics from JIIT in 2018.

Joined Center for development of Advanced Computing (CDAC Noida)  in 2007 as a lecturer. In 2008, joined JIIT as a lecturer. Currently working as an Assistant Professor (Senior Grade) in department of Electronics and Communication at JIIT.

Work Experience

12 years (teaching+research)

Interest Area(s)

Full custom design, CMOS Digital VLSI Design.


International Journals:

  • S. Kalra, " An Insight into Temperature Inversion Using α-Power MOSFET Model for Ultradeep Submicron Digital CMOS Technologies", AEU-International Journal of Electronics and Communications, vol. 125, p.153349, July 2020 .
  • S. Kalra and A.B. Bhattacharyya, "A Unified Analytical Transregional MOSFET Model for Nanoscale CMOS Digital Technologies", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol 33, issue 1, Jan 2020.
  • S. Kalra,"On the mathematical insight of moderate inversion for ultradeep submicron CMOS technologies", Journal of Computational Electronics, vol. 15, pp 1-5, 2018.
  • Kalra S, A.B. Bhattacharyya,“Scalable α-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design”, AEU-International Journal of Electronics and Communications,vol. 83 no. 1, pp 180-187, 2018.
  • S. Kalra and A. Bhattacharyya, “Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold,” International Journal of Electronics and Telecommunications, vol. 63, no. 4, pp. 369-374, 2017. 
  • Sharma, S. Kalra,”Study of Temperature Dependent Ultra Low Power Deep Submicron Digital CMOS Logic”, Journal of Energy Research and Environmental Technology(JERET), vol 4, no.1, pp. 29-31, 2017.
  • N. Narula, S. Kalra,”High Performance Low Power Arithmetic and Logic Unit: A Trade off”, Journal of Energy Research and Environmental Technology (JERET), vol 4, no.1, pp. 23-28, 2017.
  • S. Kalra, A. B. Bhattacharyya, "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α–Power MOSFET Model." Journal of Integrated Circuits and System, vol. 11, no. 1, pp. 57-68, 2016.


  • Pratul Singh, Arti Noor, Shruti Sabharwal , “Utilizing transaction level modeling in systemC to model serial interfaces”, Proceedings of 2nd national conference Mathematical techniques: Emerging paradigms for electronics and IT industries. 26th – 28th Sep. 2008.
  • S. Sabharwal, A. Noor , "An area efficient Implementation of Reed-Solomon Encoder for DVB-H Protocol”, Proceedings of 2nd national conference of resent trends in information systems (RETIS-2008), Jadavpur University Calcutta,7-9 Feb 2008.
  • Syed MurtuzaHasnain, Nikhil Ahuja, Arti Noor, Shruti Sabharwal , "Comparative Analysis of Subthreshold Leakage Reduction techniques using stack and VTCMOS technique" Proceedings of National conference on modern trends in electronics and communication systems (MTECS-2008), AMU, Aligarh, 8-9th March 2008.
  • Nikita Gupta, Rohit Tripathi, Shruti Sabharwal , “Design Methodology of standard cell library for sub-micron technology”, Proceedings of 4th National Conference on VLSI, Embedded System, Signal Processing and Communication Technologies, April 2011.
  • Kalra, S., "Effect of temperature dependence on performance of Digital CMOS circuit technologies," International Conference on Signal Processing and Communication (ICSC-2013) December 12-14, 2013, JIIT NOIDA, India.
  • S. Kalra, "A Graphical Insight into α Power MOSFET Model for Nanoscale CMOS Digital Technologies," 2020 IEEE 6th International Conference on Signal Processing and Communication (ICSC), Noida, India, 2020, pp. 325-330, doi: 10.1109/ICSC48311.2020.9182772.

Book Chapter

Kalra S, Bhattacharyya AB,“Variability Study Using α-Power-Based MOSFET Model for Ultradeep Submicron Digital Circuit Design”,  InAdvances in Signal Processing and Communication 2019 (pp. 601-610). Springer, Singapore.

Professional Projects / Professional Achievements

Title of Research Project: Mixed Signal test structures for CMOS Temperature sensor using Mentor Graphics Design Environment.

Details of Sponsoring Agency : MENTOR GRAPHICS India

Sanction Date: March 2012

Completion Date: Aug 2015