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Jaypee Institute of Information Technology, Noida
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  • Dr. Rachna Singh
Assistant Professor (Senior Grade)
rachna.singh@jiit.ac.in

Education

  • Ph.D. [Electronics and Communication Engineering (VLSI & Embedded System)] from Maulana Azad National Institute of Technology, Bhopal, Madhya Pradesh, India, in 2018.
  • M.Tech. [Electronics and Communication Engineering (VLSI & Embedded System)] from Maulana Azad National Institute of Technology, Bhopal, Madhya Pradesh, India, in 2010.
  • B.E. [Electronics and Communication Engineering] IPST, Chitrakoot, Madhya Pradesh, India, in 1998.

WORK EXPERIENCE

15 years (teaching+research)

BIOGRAPHY

Rachna Singh has been born and brought up in Rewa, Madhya Pradesh, India. After doing her graduation in 1998, she joined Shree Institute of Science and Technology as a lecturer in September, 2002, after working there for 4 years, she joined Sagar Institute of Science and Technology as Assistant professor. Then she did her M.Tech. and Ph.D. in 2010 and 2018 respectively. Since then she isengaged in research and development in the field of VLSI & Embedded System. She has several International and National journal publications in reputed journals.

INTEREST AREAS

  • VLSI
  • Digital circuits
  • Microprocessors
  • Electronic devices and circuits
  • Embedded System.

RESEARCH INTERESTS

  • FPGA designing
  • Hardware software Co design
  • VLSI

PUBLICATIONS

INTERNATIONAL JOURNALS

  • One international paper titled “Implementation of Immune Genetic Algorithm for Generating Test Pattern in VLSI Circuits” published in IJAC, Hyderabad (international journal of advance computing), vol. 2, Issue 3, July 2010.
  • One international paper titled “Implementation of genetic algorithm for automatic test pattern generation” published In IJSER (International journal of Scientific and Engineering Research), vol 3,Issue 4, April 2012.
  • One international paper titled “A Review of FPGA-based design methodologies for efficient hardware Area estimation” published In IOSR (International Organization of Scientific Research), vol 4, Issue 4, April 2013.
  • One international paper titled “Accurate Area estimation model for FPGA based
  • Implementation” Journal of VLSI & Signal Processing, vol.6, pp. 26-32, issue 4, Ver. II (Jul-Aug. 2016).
  • One international paper titled “Analytical Model for High-Level Area Estimation of FPGA Design” International Journal of Embedded and Real-Time Communication Systems (IJERTCS), vol.7, issue 2, (May-June 2017).
  • One international paper titled “High-Level Area Estimation Model for FPGA based Designs using LLVM” International Journal of Electronics (IJE) accepted.

REVIEWER

  • IGI global transaction in International Journal of Embedded and Real-Time Communication Systems (IJERTCS)

WORKSHOP/NATIONAL SEMINAR

  • Workshop on “ Signals & System” at IIT Kharagpur dated 15 th Sep 2013 to 21 st Sep 2013
  • Workshop on “ Optimization Techniques” MANIT, Bhopal dated 10 th Dec 2012 to 11 th Dec 2012
  • Staff development program on” Nano Technology” at SIRT, Bhopal dated 13-25 June 2011.
  • Training Course on “ EMBEDDED SYSTEM” at CRISP, Bhopal dated 10-14 NOV 2008.
  • Workshop on” MATLAB” at SIRT, Bhopal dated 19-24 JAN, Bhopal.
  • National Seminar on “VLSI & EMBEDDED SYSTEM” AT OIST, Bhopal dated 30-31MAR 2007.

OTHERS:

She was ISTE Remote Centre Coordinator for the conduction of workshop from IIT Bombay & IIT Kharagpur at SISTec-E, Bhopal. Also as a Remote Centre Coordinator following workshops were organized by her:

  • Workshop on “Data base management” by IIT Bombay
  • Workshop on “Engineering Mechanics” by IIT Bombay
  • Workshop on “Signals & System” by IIT Kharagpur
  • Workshop on “Computer Programming” by IIT Bombay
  • Workshop on “Computer Networking” by IIT Bombay
  • Aakash project coordinator for the Aakash tablets Usage and maintenance.