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Jaypee Institute of Information Technology, Noida
Assistant Professor (Grade-II)
mandeep.narula@jiit.ac.in

Education

  • M.Tech, Microelectronics & VLSI, IIT Kharagpur (2006-2008)
  • B.Tech, Electronics & Communication Engineering, Kurukshetra University (2001-2005)

Biography

   Total Teaching Experience – 6+ Years

   Total Industry Experience – 2 Years 

Work Experience

  • Assistant Professor – II, JIIT, Sec 62 Noida,  (October 2015 – Present)
  • Assistant Professor  – II, G.D Goenka University, Gurgaon (June 2013 – October 2015)
  • Assistant Professor, ITM University, Gurgaon (January 2011 – June 2013)
  • Assistant Professor, AKGEC affiliated to UPTU (July 2010 – December 2010)
  •  VLSI Consultant in Transwitch, Delhi (2009 – 2010)
  • Senior Member Technical Staff in Mentor Graphics, Noida (2008-2009) 

Interest Area(s)

CMOS Digital Design, RTL Design, Analog Circuit Design, High Speed and Low Power CMOS Circuits, Digital System Design with VHDL/Verilog. 

Publications

International Journals

  1. Mandeep Singh Narula, Ramandeep Singh, “Verilog Implementation, Synthesis & Physical Design of MOD 16 Counter”, International Journal of Engineering Sciences & Research Technology, Vol 3, Issue 10, October 2014
  2. Mandeep Singh Narula, Simarpreet Singh, “Implementation of Triple Data       Encryption Standard using Verilog”, International Journal of Advanced Research in Computer Science and Software Engineering, Vol 3, Issue 12, pp 1172-1177, January 2014
  3. Manish Choudhary, Mandeep Singh Narula, “FPGA implementation of Booth's and Baugh-Wooley Mutiplier Using Verilog”, International Journal of Innovative Technology and Exploring Engineering, Vol 3, Issue 1, pp.   , May 2013
  4. Manish Choudhary, Mandeep Singh Narula, “High Speed Modified Booth’s Multiplier for Signed and Unsigned Numbers”, International Journal of Science and Engineering Investigations, Vol 2, Issue 12, pp. 106-113, January 2013
  5. Mandeep Singh Narula, Pankaj Rakheja, Charu Rana, “Giga bit per second Differential Scheme for High Speed Interconnect” International Journal of VLSI Design & Communication Systems, Vol.3, No.1, February 2012
  6. Charu Rana, Pankaj Rakheja, Mandeep Singh Narula, “Mechanism for Enhancing the Overall Performance of Multicore Processors”, International Journal of Scientific and Engineering Research, February 2012

International Conferences

  1. Mandeep Singh Narula, “Transmitter for High Speed I/O using Current Mode Signalling” presented at the International Conference on VLSI, MEMS and NEMS held at Amity University, Noida on 24th and 25th  Jan 2012
  2. Pankaj Rakheja, Mandeep Singh Narula, “Design of 8T, 10T & 28T High Speed Low Power Full Adder”, International Conference on Recent Developments in Science, Engineering and Technology, October 2015
  3. Navneet Sharma, Mandeep Singh Narula, “Colored Balls Sorting & Counting Using Microcontroller”, International Conference on Recent Developments in Science, Engineering and Technology, October 2015
  4. Shreya Prakash, Mandeep Singh Narula, “Implementation of High Speed Digital NMOS Input Buffer Design”, International Conference on Recent Developments in Science, Engineering and Technology, October 2015
  5. Nankita Asija, Renu Saini, Pankaj Rakheja and Mandeep Narula, “A Unique Circle Cipher Approach using Audio Stenography for Network Security”, International Conference on Recent Developments in Science, Engineering and Technology, October 2015

National Conferences

  1. Mandeep Singh Narula, Ramandeep Singh, “Implementation of DLL based Serializer”, presented at the National Conference on Recent Developments in Science, Engineering and Technology, 17-18 October 2014, G D Goenka University, Gurgaon
  2. Ramandeep Singh, Mandeep Singh Narula, Kandla Arora, “Strategizing PWM Application for LED Based Industrial Testing Light Panels”, National Conference on Recent Developments in Science, Engineering and Technology, 17-18 October 2014, G D Goenka University, Gurgaon
  3. Manish Choudhary, Mandeep Singh Narula, “An Efficient Implementation Technique for 8 Bit and 16 Bit Binary Multiplication Using Verilog”, National Conference on Contemporary Techniques & Technologies held at DCRUS&T, Murthal, March 2013

Achievements

  • Secured 99.80 percentile (AIR – 125) in GATE 2006 exam
  • Secured 98.14 percentile in GATE 2005 exam
  • GATE Fellowship for M.Tech. (VLSI) programme, Indian Institute of Technology, Kharagpur, (Awarded by Ministry of Human Resource Development (MHRD), Govt. of India) for 2006-2008.
  • Awarded with Certificate of Appreciation for conducting Workshops on RTL Design and Verification & Virtual Labs
  • Reviewer of VLSICS Journal - International Journal of VLSI Design & Communication Systems
  • Reviewer of Journal of Semiconductor
  • Completed Online Course – Control of Mobile Robots (Georgia Institute of Technology, with distinction – 88.6%), Jan 2014 - March 2014
  • Completed Online Course – Solar Cell, Fuel Cell & Batteries (Stanford University), Sept 2013 - Dec 2013

Workshop & Conferences Attended

  • Attended Six Days Workshop on Open Source Alternatives for Engineering in July 2015
  • Attended One Day FDP on Effective Mentoring in Dec 2014
  • Attended Two Days Workshop on Robotix, in Jan 2014 conducted by Sparklab Engineering System (affiliated with IIT Guwahati)
  • Attended One Day Workshop on Networking & Security, Nov 2013 conducted by Network Bulls
  • Attended Two Days Faculty Development Program conducted by Advait Life Education Pvt Ltd, Noida in July 2012
  • Attended One Day Training Program on Virtual Lab held in May 2012 at IIT Delhi
  • Attended Three Days Workshop on NEN (National Entrepreneurship Network) Faculty Development Programme held during 19th – 21st August 2011 at JIMS, Delhi
  • Attended One Day NEN Orientation Program on 8th July 2011 at ITM University
  • Attended Two Days Workshop on Deployment and Use of NPTEL (National Programme on Technology Enhanced Learning) held in October 2010 at JSS Academy of Tech Education, Noida 
  • Attended Two Days Training Program on Virtual Lab held in September 2010 at IIT Delhi