M.Tech – Indian Institute of Technology (BHU), Varanasi (2014)
B.Tech - Krishna Institute of Engineering & Technology, Ghaziabad (2011)
- Qualified joint CSIR-UGC NET-2014 December with AIR-06 in Engineering Science
- Qualified GATE-2014 with AIR-736 and 99.66 percentile.
- Qualified GATE-2012 with AIR-422 and 99.76 percentile
Mr. Varun Goel received his M.Tech from Indian Institute of Technology (BHU) Varanasi with specialization in Microelectronics in 2014. He completed his B.Tech from Uttar Pradesh Technical University, Lucknow in 2011. He has been associated with Jaypee Institute of Information Technology, Noida as an Assistant Professor from Aug 2015.
Semiconductor Device modeling and simulation, Solid State devices, Digital Logic Design
- Varun Goel; Sanjay Sharma; Sanjay Kumar; S. Jit. (2014, December). “Two-dimensional analytical model for threshold voltage of graded-channel SOI MOSFETs”. in 2014 IEEE 2nd International Conference on Emerging Electronics (ICEE), (pp. 1-4).
- Varun Goel; Sanjay Sharma (2016 December) “Study of role of channel engineering in dual-material-double-gate MOSFETs”, in 2016 IEEE 11th International Conference on Industrial and Information Systems (ICIIS) (pp. 778-783).
- Varun Goel; Anuj Kumar Maurya; Sanjay Sharma; Sanjay Kumar (2016 December) “Study of role of channel engineering and gate engineering in silicon-on-insulator (SOI) MOSFETs using 2-D analytical modeling”, in 2016 IEEE 3rd International Conference on Emerging Electronics (ICEE) (pp. 1-5).
- Varun Goel; Abhay Kumar; Sidhartha Sankar Rout; Anuj Kr Maurya; Sanjay Sharma; Sanjay Kumar (2016 December) “2-D analytical model of surface potential for graded-channel-double-gate (GCDG) MOSFETs”, in 2016 IEEE International Conference on Signal Processing and Communication (ICSC) (pp. 1-5).