Ph. D (JIIT, Noida), M.Tech (IIT Delhi), B. Tech(A.M.U)
Shamim Akhter was born at Chittaranjan, West Bengal, India on January 15, 1979. He received B.Tech degree from ZHCET, AMU(June 2001), M.Tech degree from IIT Delhi (Dec 2002) and Ph.D degree from Jaypee Institute of Information Technology, Noida, India(March 2015). He joined Jaypee Institute of Information Technology, Noida, in April 2003 as a Lecturer. Since then he is engaged in teaching, research and development in the field of VLSI digital circuits design. He has published research papers in reputed International Journals. Besides he has also published papers in International Conferences in India and abroad. Presently he is Assistant Professor in the Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Sector 62, Noida.
VLSI Circuit and System Design, VLSI Signal Processing, HDL design, FPGA
Experience: 16 years (teaching + research)
- S. Akhter: Digital Hardware Design, university Science Press, 2008.
- S.Akhter: Fundamentals of Digital Systems, Vikas Publication House Pvt Ltd, 2009.
- S,Akhter and T.Chauhan: Basic Electronics Engineering, Pearson, 2014.
- S.Akhter, G. Raturi, S.Khan, " Analysis and Design of Residue Number System Based Building Blocks, at 5th International Conference on Signal Processing Integrated Network, 22-23rd Feb 2018, pp.441-445[ (IEEExplorer)
- A.Bhardwaj, S.Akhter" IP Protection of sequential circuits using added states watermark with property implantation, Advances in signal processing and communication, Proceeding of International Conference on Signal Processing and Communication,(21-23 March 2018)
- S. Akhter, V. Karwal, and R. C. Jain, “Improved Algorithm for ODCT Computation of a Running Data Sequence,” Journal of Electrical and Computer Engineering, vol. 2012, Article ID 879626, 10 pages, 2012. doi:10.1155/2012/879626.[Indexed in SCOPUS]
- S. Akhter, V. Karwal, and R. C. Jain “Fast Windowed Update Algorithm for ODCT Computation,” International Journal of Electronics Letters, Taylor & Francis, doi:10.1080/21681724.2014.880989, vol. 2, no. 2, 2014.
- S.Akhter and S. Chaturvedi, “A High Speed 14 Transistor Full Adder Cell Using Novel 4-Transistor XOR / XNOR Gates Based on Dynamic CMOS Logic”, International Journal of Applied Engineering Research, Volume 9, Number 11 (2014) pp. 1551-1564.[Indexed in SCOPUS].
- Vikas K. Saini, Shamim Akhter, and Tanuj Chauhan, "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits," VLSI Design, vol. 2016, Article ID 1260879, 2016. doi:10.1155/2016/1260879.
- Anshul Singh, Vijay KhareShaurya Singh, Neha Mehra, Chakras Jain, Shamim Akhter, "Analysis and Identification of Parkinson disease based on fMRI", International Journal of Engineering Technology , Management and Applied Sciences, Vol 5,Issue 1, 2017, ISSN 2349-4476.
- Hemant K., Hamsavahini, Upadhyay P., and Akhter, S., “Design and implementation of crypto-based inter leaver for viterbi encoder and decoder using turbo codes”, in 7th International Conference on ASIC Proceeding ASICON, art. no. 4415778, pp. 906-909, Oct. 2007.[Indexed in SCOPUS]
- Akhter, S., “VHDL implementation of fast NxN multiplier based on Vedic mathematic”, in 18th European Conference on Circuit Theory and Design, Sevilla, Spain, pp. 472-475, 26-30 August , 2007.[Indexed in SCOPUS]
- Gupta, N., Gupta, S., Khare, V., Jain, C. K., and Akhter, S., “An efficient model to decipher the Electroencephalogram signals using machine learning approach”, in Biomed 2008 (4th Kuala Lumpur International Conference on Biomedical Engineering 2008), Kualalumpur, Malysia, published in IFMBE Proceedings , Vol. 21, 2008, pp.782-785, June 2008. [Indexed in Web of Science]
- S.Akhter, V.Karwal, and R.C.Jain , “Implementation of Odd Discrete Cosine Transform (ODCT-II) using Distributed Arithmetic Approach”, in Proceeding of 3rd Nirma University International Conference on Engineering NUiCONE-2012, Nirma University, Ahmedabad, 2012. (IEEExplorer)
- S.Akhter, V.Karwal, and R.C.Jain, “Implementation of Rectangular Windowed Odd Discrete Cosine Transform Update Algorithm Using Distributed Arithmetic Approach", International Conference on Signal Processing and Communication (ICSC-2013) December 12-14, 2013, pp. 381-386, JIIT NOIDA, India. (IEEExplorer)
- S.Akhter and S. Chaturvedi,“HDL Based Implementation of NxN Bit-Serial Multiplier,” Proc. of IEEE International Conference on Signal Processing and Integrated Networks (SPIN-2014), pp. 470-474, Feb. 20-21, 2014, Amity University, NOIDA, India. (IEEExplorer)
- S.Akhter and S. Chaturvedi, “A Novel Method for Dual Output Dynamic Logic Using SCL Topology,” Proc. of IEEE International Conference on Signal Processing and Integrated Networks (SPIN-2014), pp. 481-485, Feb. 20-21, 2014, Amity University, NOIDA, India. (IEEExplorer)
- S.Akhter, S. Chaturvedi, and K.Pardhasardi, “CMOS Implementation of Efficient 16-Bit Square Root Carry-Select Adder,“ 2nd International Conference on Signal Processing and Integrated Networks (SPIN), India, Noida, pp. 891 – 896, Feb 2015(IEEExplorer)
- Shamim Akhter, Vikas K. Saini, Jasmine Saini, "Analysis of Vedic Multiplier using Various Adder Topologies", 4th International Conference on Signal Processing and Integrated Networks SPIN , Amity University, India, pp-173-176 March 2017 (IEEExplorer)